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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
SST32HF202 / 402 / 8022Mb Flash + 2Mb SRAM, 4Mb Flash + 2Mb SRAM, 8Mb Flash + 2Mb SRAM (x16) MCP ComboMemory
Data Sheet
FEATURES:
* MPF + SRAM ComboMemory - SST32HF202: 128K x16 Flash + 128K x16 SRAM - SST32HF402: 256K x16 Flash + 128K x16 SRAM - SST32HF802: 512K x16 Flash + 128K x16 SRAM * Single 2.7-3.3V Read and Write Operations * Concurrent Operation - Read from or write to SRAM while Erase/Program Flash * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 15 mA (typical) for Flash or SRAM Read - Standby Current: 20 A (typical) * Flexible Erase Capability - Uniform 2 KWord sectors - Uniform 32 KWord size blocks * Fast Read Access Times: - Flash: 70 ns - SRAM: 70 ns * Latched Address and Data for Flash * Flash Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Word-Program Time: 14 s (typical) - Chip Rewrite Time: SST32HF202: 2 seconds (typical) SST32HF402: 4 seconds (typical) SST32HF802: 8 seconds (typical) * Flash Automatic Erase and Program Timing - Internal VPP Generation * Flash End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Conforms to Flash pinout * Packages Available - 48-ball LFBGA (6mm x 8mm) - 48-ball LBGA (10mm x 12mm) (SST32HF802 only) * All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF202/402/802 ComboMemory devices integrate a 128K x16, 256K x16, 512K x16 CMOS flash memory bank with a 128K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST's proprietary, high performance SuperFlash technology. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 14 sec. The entire flash memory bank can be erased and programmed word-by-word in typically 2 seconds for the SST32HF202, 4 seconds for the SST32HF402, and 8 seconds for the SST32HF802, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST32HF202/402/802 devices contain onchip hardware and software data protection schemes. The SST32HF202/402/802 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HF202/402/802 devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both
(c)2005 Silicon Storage Technology, Inc. S71209-06-000 5/05 1
memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST32HF202/402/802 provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet The SST32HF202/402/802 devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF202/402/802 devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST32HF202/402/802 inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
SRAM Read
The SRAM Read operation of the SST32HF202/402/802 is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 3 for the Read cycle timing diagram.
SRAM Write
The SRAM Write operation of the SST32HF202/402/802 is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The write time is measured from the last falling edge to the first rising edge of BES# or WE#. See Figures 4 and 5 for the Write cycle timing diagrams.
Flash Operation
With BEF# active, the SST32HF202 operates as 128K x16 flash memory, the SST32HF402 operates as 256K x16 flash memory, and the SST32HF802 operates as 512K x16 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and during the internally-timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is activated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high.
Flash Read
The Read operation of the SST32HF202/402/802 devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 6 for further details.
SRAM Operation
With BES# low and BEF# high, the SST32HF202/402/802 operate as 128K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST32HF202/402/802 SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high, both memory banks are deselected and the device enters standby mode. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM Read and Write data byte control modes of operation.
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST32HF202/402/ 802. SDP commands are loaded to the flash memory bank using standard microprocessor Write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first.
SST32HF202, A17-A15, for SST32HF402, and A18-A15, for SST32HF802, are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 12 and 13 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.
Flash Word-Program Operation
The flash memory bank of the SST32HF202/402/802 devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored.
Flash Chip-Erase Operation
The SST32HF202/402/802 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF202/402/802 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF202/402/802 offer both SectorErase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A16-A11, for SST32HF202, A17-A11, for SST32HF402, and A18-A11, for SST32HF802, are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines A16-A15, for
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Flash Data# Polling (DQ7)
When the SST32HF202/402/802 flash memory banks are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles, after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 19 for a flowchart.
Flash Software Data Protection (SDP)
The SST32HF202/402/802 provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF202/402/802 devices are shipped with the software data protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the Read mode, within Read cycle time (TRC).
Concurrent Read and Write Operations
The SST32HF202/402/802 provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the Flash. This allows data alteration code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states. CONCURRENT READ/WRITE STATE TABLE
Flash Program/Erase Program/Erase SRAM Read Write
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `1's and `0's, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 19 for a flowchart.
Flash Memory Data Protection
The SST32HF202/402/802 flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes.
The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down.
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Product Identification
The Product Identification mode identifies the devices as the SST32HF202/402/802 and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 14 for the software ID entry and Read timing diagram, and Figure 20 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST32HF202 SST32HF402 SST32HF802 0001H 0001H 0001H 2789H 2780H 2781H
T1.2 1209
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 15 for timing waveform and Figure 20 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin.
Data 00BFH
0000H
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
AMS-A0
UBS# LBS# BES# BEF# OE# WE#
Control Logic
I/O Buffers
DQ15 - DQ8 DQ7 - DQ0
Address Buffers & Latches
SuperFlash Memory
1209 B1.0
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
SST32HF202
SST32HF402
6 5 4 3 2 1
A13 A9 WE# BES# A7 A3
A12 A8 NC NC NC A4
A14 A10 LBS# NC A6 A2
A15 A11 NC NC A5 A1
A16 UBS# DQ15 VSS DQ7 DQ14 DQ13 DQ6 DQ5 DQ12 VDD DQ4
1209 48-lfbga L3K P1a.3
6 5 4
A13 A9 WE#
A12 A8 NC NC A17 A4
A14 A10 LBS# NC A6 A2
A15 A11 NC NC A5 A1
A16 UBS# DQ15 VSS DQ7 DQ14 DQ13 DQ6 DQ5 DQ12 VDD DQ4 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 DQ9 DQ1 A0 BEF# OE# VSS
1209 48-lfbga L3K P1b.3
DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 DQ9 DQ1 A0 BEF# OE# VSS
3
BES#
2
A7
1
A3
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
TOP VIEW (balls facing down)
SST32HF802
6 5 4
A13 A9 WE#
A12 A8 NC NC A17 A4
A14 A10 LBS# A18 A6 A2
A15 A11 NC NC A5 A1
A16 UBS# DQ15 VSS DQ7 DQ14 DQ13 DQ6 DQ5 DQ12 VDD DQ4 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 DQ9 DQ1 A0 BEF# OE# VSS
1209 48-lfbga L3K P1c.3
3
BES#
2
A7
1
A3
A
B
C
D
E
F
G
H
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TOP VIEW (balls facing down)
SST32HF802
6 5 4 3 2
BES# VSS DQ1 A10 DQ5 DQ2 OE# DQ7 DQ4 A11 A13 A8 A5
A1 A0 DQ0 DQ8
A2 A3 A6
A4 A7 A18
NC NC NC
A9 A14 A15
DQ3 DQ12
A12 LBS# DQ6 DQ15 1209 48-tbga LBK P2.0
A17 UBS# BEF# DQ10 VDDF VSS
1
WE# VDDS A16 DQ9 DQ11 DQ13 DQ14
ABCDEFGH
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM)
TABLE 2: PIN DESCRIPTION
Symbol AMS1-A0 DQ15-DQ0 Pin Name Address Inputs Data Input/output Functions To provide flash addresses, A16-A0 for 2M, A17-A0 for 4M, and A18-A0 for 8M. To provide SRAM addresses, A16-A0 for 2M. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. To activate the SRAM memory bank when BES# is low. To activate the Flash memory bank when BEF# is low. To gate the data output buffers. To control the Write operations. 2.7-3.3V power supply (for L3K package only) 2.7-3.3V power supply to flash only 2.7-3.3V power supply to SRAM only To enable DQ15-DQ8 To enable DQ7-DQ0 Unconnected Pins
T2.4 1209
BES# BEF# OE# WE# VDD VDDF2 VDDS2 VSS UBS# LBS# NC
SRAM Memory Bank Enable Flash Memory Bank Enable Output Enable Write Enable Power Supply Power Supply (Flash) Power Supply (SRAM) Ground Upper Byte Control (SRAM) Lower Byte Control (SRAM) No Connection
1. AMS = Most significant address 2. For SST32HF802 in the LBK package only
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet TABLE 3: OPERATION MODES SELECTION
Mode Not Allowed Flash Read Program Erase SRAM Read VIL VIL VIL Write VIL VIL VIL Standby Flash Write Inhibit VIHC X X X Output Disable VIH VIL VIL Product Identification Software Mode VIH VIL VIL VIH X X Manufacturer's ID (00BFH) Device ID3 AMSF4-A1=VIL, A0=VIH (See Table 4)
T3.5 1209
BES#1 BEF#1 OE# WE# UBS# LBS# VIL VIH VIH X VIL VIL VIL VIL X2 VIL VIH VIH X VIH VIL VIL X X X X X X X X
DQ15 to DQ8 X DOUT DIN X
DQ7 to DQ0 X DOUT DIN X
Address X AIN AIN Sector or Block address, XXH for Chip-Erase AIN AIN AIN AIN AIN AIN X X X X X X X
VIH VIH VIH VIH VIH VIH VIHC X X VIH VIL VIH VIH
VIL VIL VIL X X X X VIL X X VIH X VIH
VIH VIH VIH VIL VIL VIL X X VIH X VIH X VIH
VIL VIL VIH VIL VIL VIH X X X X X VIH X
VIL VIH VIL VIL VIH VIL X X X X X VIH X
DOUT DOUT High Z DIN DIN High Z High Z
DOUT High Z DOUT DIN High Z DIN High Z
High Z / DOUT High Z / DOUT High Z / DOUT High Z / DOUT High Z / DOUT High Z / DOUT High Z High Z High Z High Z High Z High Z
1. 2. 3. 4.
Do not apply BES#=VIL and BEF#=VIL at the same time X can be VIL or VIH, but no other value. Device ID for: SST32HF202 = 2789H, SST32HF402 = 2780H, and SST32HF802 = 2781H AMS = Most significant flash address
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software ID Exit Software ID Exit 1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T4.4 1209
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data 55H 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data A0H 80H 80H 80H 90H
4th Bus Write Cycle Addr1 WA2 5555H 5555H 5555H Data Data AAH AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data 55H 55H 55H
6th Bus Write Cycle Addr1 SAX3 BAX
3
Data 30H 50H 10H
5555H
Software ID Entry4,5 5555H
1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence. 2. WA = Program Word address 3. SAX for Sector-Erase; uses AMS-A11 address lines BAX for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A16 for SST32HF202, A17 for SST32HF402, and A18 for SST32HF802 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0 = 0, SST32HF202 Device ID = 2789H, is read with A0 = 1, SST32HF402 Device ID = 2780H, is read with A0 = 1 SST32HF802 Device ID = 2781H, is read with A0 = 1.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Extended Ambient Temp 0C to +70C -20C to +85C VDD 2.7-3.3V 2.7-3.3V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 16 and 17
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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits Symbol IDD Parameter Power Supply Current Read Flash SRAM Concurrent Operation Write Flash SRAM ISB Standby VDD Current SST32HF202/402 SST32HF802 ILI ILO VIL VIH VIHC VOLF VOHF VOLS VOHS Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input High Voltage (CMOS) Flash Output Low Voltage Flash Output High Voltage Output Low Voltage Output High Voltage 2.2 VDD-0.2 0.4 0.7 VDD VDD-0.3 0.2 30 40 1 10 0.8 A A A A V V V V V V V VDD=VDD Max, BEF#=BES#=VIHC VDD=VDD Max, BEF#=BES#=VIHC VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min IOL=1 mA, VDD=VDD Min IOH=-500 A, VDD=VDD Min
T5.7 1209
Min
Max
Units
Test Conditions Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open
30 30 55 30 30
mA mA mA mA mA
OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL WE#=VIL BEF#=VIL, BES#=VIH, OE#=VIH BEF#=VIH, BES#=VIL
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T6.0 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (TA = 25C, f=1 Mhz, other pins open)
Parameter CI/O
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 24 pF 12 pF
T7.0 1209
CIN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: FLASH RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T8.0 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
10
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
AC CHARACTERISTICS
TABLE 9: SRAM READ CYCLE TIMING PARAMETERS
Symbol TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS
1
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# to Active Output Output Enable to Active Output UBS#, LBS# to Active Output BES# to High-Z Output Output Disable to High-Z Output UBS#, LBS# to High-Z Output Output Hold from Address Change
Min 70
Max 70 70 35 70
Units ns ns ns ns ns ns ns ns
0 0 0 25 0 10 25 35
ns ns ns ns
T9.3 1209
TOHZS1 TBYHZS1 TOHS
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS
Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# to End-of-Write Output Disable from WE# Low Output Enable from WE# High Data Set-up Time Data Hold from Write Time 0 30 0 Min 70 60 60 0 60 0 60 30 Max Units ns ns ns ns ns ns ns ns ns ns ns
T10.3 1209
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
11
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet TABLE 11: FLASH READ CYCLE TIMING PARAMETERS
Symbol TRC TBE TAA TOE TBLZ1 TOLZ1 TBHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Bank Enable Access Time Address Access Time Output Enable Access Time BEF# Low to Active Output OE# Low to Active Output BEF# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 20 20 Min 70 70 70 35 Max Units ns ns ns ns ns ns ns ns ns
T11.2 1209
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TBS TBH TOES TOEH TBPW TWP TWPH TBPH TDS TDH TIDA TSE TBE TSCE Parameter Word-Program Time Address Setup Time Address Hold Time WE# and BEF# Setup Time WE# and BEF# Hold Time OE# High Setup Time OE# High Hold Time BEF# Pulse Width WE# Pulse Width WE# Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase 0 30 0 0 0 10 40 40 30 30 30 0 150 25 25 100 Min Max 20 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
T12.0 1209
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
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12
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TRCS ADDRESSES AMSS-0 TAAS BES# TBES TBLZS OE# TOLZS UBS#, LBS# TBYLZS DQ15-0 DATA VALID
1209 F02.0
TOHS
TBHZS TOES TOHZS TBYES TBYHZS
Note: WE# remains High (VIH) for the Read cycle AMSS = Most Significant SRAM Address
FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM
TWCS ADDRESSES AMSS-0 TASTS TWPS TWRS
WE# TAWS TBWS BES#
TBYWS UBS#, LBS# TODWS DQ15-8, DQ7-0 NOTE 2 TOEWS TDSS TDHS NOTE 2
1209 F03.1
VALID DATA IN
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance. If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
(c)2005 Silicon Storage Technology, Inc. S71209-06-000 5/05
13
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TWCS ADDRESSES AMSS-0 TWPS WE# TWRS
TBWS BES# TAWS TASTS TBYWS
UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE 2 TDHS NOTE 2
1209 F04.0
VALID DATA IN
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
TRC ADDRESSES AMSF-0
TAA
BEF#
TBE
OE# VIH WE# TOLZ
TOE
TOHZ TBHZ HIGH-Z DATA VALID
1209 F05.0
DQ15-0
HIGH-Z
TBLZ
TOH DATA VALID
AMSF = Most Significant Flash Address
FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
14
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESSES AMSF-0 5555 TAH TWP WE# TAS OE# TCH BEF# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA)
1209 F06.0
2AAA
5555
ADDR TDH
TWPH
TDS
AMSF = Most Significant Flash Address Note: X can be VIL or VIH, but no other value
FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESSES AMSF-0 5555 TAH TCP BEF# TAS OE# TCH WE# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
AMSF = Most Significant Flash Address Note: X can be VIL or VIH, but no other value
1209 F07.0
FIGURE 8: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
15
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
ADDRESSES AMSF-0 TCE BEF# TOEH OE# TOE WE# TOES
DQ7
Data
Data#
Data#
Data
1209 F08.0
AMSF = Most Significant Flash Address
FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESSES AMSF-0 TBE BEF# TOEH OE# TOE TOES
WE#
DQ6
AMSF = Most Significant Flash Address
TWO READ CYCLES WITH SAME OUTPUTS
1209 F09.0
FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
16
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMSF-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX10 SW5
1209 F10.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value AMSF = Most Significant Flash Address
FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
SIX-WORD CODE FOR SECTOR-ERASE ADDRESSES AMSF-0 5555 2AAA 5555 5555 2AAA SAX
TSE
BEF#
OE# TWP WE#
DQ15-0
XXAA SW0
Note:
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX30 SW5
1209 F11.0
The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value SAX = Sector Address AMSF = Most Significant Flash Address
FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
17
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
SIX-WORD CODE FOR BLOCK-ERASE ADDRESSES AMSF-0 5555 2AAA 5555 5555 2AAA BAX
TBE
BEF#
OE# TWP WE#
DQ15-0
XXAA SW0
Note:
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX50 SW5
1209 F12.1
The device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value BAX = Block Address AMSF = Most Significant Flash Address
FIGURE 13: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
THREE-WORD SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 SW2 TAA 00BF MFG ID
1209 F13.4
TIDA
DEVICE ID
Note: X can be VIL or VIH, but no other value Device ID = 2789H for SST32HF202, 2780H for SST32HF402, 2781H for SST32HF802
FIGURE 14: SOFTWARE ID ENTRY AND READ
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
18
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
THREE-WORD SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
OE# TWP WE# T WHP SW0
Note:
SW1
SW2
1209 F14.0
X can be VIL or VIH, but no other value
FIGURE 15: SOFTWARE ID EXIT AND RESET
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
19
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1209 F15.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 16: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
1209 F16.0
FIGURE 17: A TEST LOAD EXAMPLE
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
20
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Start
Write data: XXAAH Address: 5555H
Write data: XX55H Address: 2AAAH
Write data: XXA0H Address: 5555H
Write Word Address/Word Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1209 F17.0
X can be VIL or VIH, but no other value.
FIGURE 18: WORD-PROGRAM ALGORITHM
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
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21
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, or TBE
Read word
Read DQ7
Program/Erase Completed
Read same word
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
1209 F18.0
FIGURE 19: WAIT OPTIONS
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
22
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Software Product ID Entry Command Sequence Write data: XXAAH Address: 5555H
Software Product ID Exit & Reset Command Sequence Write data: XXAAH Address: 5555H Write data: XXF0H Address: XXXXH
Write data: XX55H Address: 2AAAH
Write data: XX55H Address: 2AAAH
Wait TIDA
Write data: XX90H Address: 5555H
Write data: XXF0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
1209 F19.0
X can be VIL or VIH, but no other value.
FIGURE 20: SOFTWARE PRODUCT COMMAND FLOWCHARTS
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
23
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address: SAX
Load data: XX50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFFFH
Sector erased to FFFFH
Block erased to FFFFH
1209 F20.0
X can be VIL or VIH, but no other value.
FIGURE 21: ERASE COMMAND SEQUENCE
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
24
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
Concurrent Operation Load SDP Command Sequence
Flash Program/Erase Initiated
Wait for End of Write Indication
Read or Write SRAM
End Wait
Flash Operation Completed
End Concurrent Operation
1209 F21.0
FIGURE 22: CONCURRENT OPERATION FLOWCHART
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
25
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
PRODUCT ORDERING INFORMATION
Device SST32HFxxx Speed - XXX Suffix1 XX Suffix2 XXXX Package Attribute E1 = non-Pb Package Modifier K = 48 balls Package Type L3 = LFBGA (6mm x 8mm x 1.4mm) LB = LBGA (10mm x 12mm x 1.4mm) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns SRAM 2 = 2 Mbit SRAM Density 20 = 2 Mbit Flash 40 = 4 Mbit Flash 80 = 8 Mbit Flash Voltage H = 2.7-3.3V Product Series 32 = MPF + SRAM ComboMemory
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
26
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet Valid combinations for SST32HF202 SST32HF202-70-4C-L3K SST32HF202-70-4C-L3KE SST32HF202-70-4E-L3K SST32HF202-70-4E-L3KE Valid combinations for SST32HF402 SST32HF402-70-4C-L3K SST32HF402-70-4C-L3KE SST32HF402-70-4E-L3K SST32HF402-70-4E-L3KE Valid combinations for SST32HF802 SST32HF802-70-4C-L3K SST32HF802-70-4C-LBK SST32HF802-70-4C-L3KE SST32HF802-70-4C-LBKE SST32HF802-70-4E-L3K SST32HF802-70-4E-LBK SST32HF802-70-4E-L3KE SST32HF802-70-4E-LBKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
27
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
6 5 4 3 2 1
0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20
6 5 4 3 2 1
A1 CORNER 1.30 0.10
SIDE VIEW
SEATING PLANE 0.35 0.05
0.12
1mm
Note:
1. Except for total height dimension, complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm)
48-lfbga-L3K-6x8-450mic-5
48-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 6MM X 8MM SST PACKAGE CODE: L3K
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
28
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet
TOP VIEW
12.00 0.20
BOTTOM VIEW
7.0 1.0
6 5 4
10.00 0.20 5.0
6 5 4 3 2 1
1.0 0.50 0.05 (48X) A B C D E F G H 1.4 Max H G F E D C B A A1 CORNER
3 2 1
A1 CORNER
SIDE VIEW
SEATING PLANE 0.40 0.05 Note:
0.12
1mm
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.4 mm ( 0.05 mm)
48-lbga-LBK-10x12-500mic-2
48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM SST PACKAGE CODE: LBK
(c)2005 Silicon Storage Technology, Inc.
S71209-06-000
5/05
29
Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
Data Sheet TABLE 13: REVISION HISTORY
Number 00 01 02 03 Description Date Feb 2002 Apr 2002 Apr 2002 Mar 2003
* * * * * * *
2002 Data Book Document Control Release (SST Internal): No technical changes Removed the 1 Mbit SRAM devices Added the 0 Mbit SRAM parts Migrated the 8 Mbit parts from S71171 to S71209 Added L3K package for 8 Mb parts Changes to Table 5 on page 10 - IDD active Read and Write current increased to 30 mA for SRAM and Flash - Test Conditions for Power Supply Current corrected - IDD active Concurrent Operation increased to 55 mA - ISB Standby current decreased to 40 A on SST32HF802 - Output leakage current increased to 10 A Removed all MPNs for 0 Mbit SRAM parts and 90 ns parts (See page 27) 2004 Data Book Updated L3K and LBK package diagrams Changed IDD test condition for frequency specification from 1/TRC Min to 5 MHz See Table 5 on page 10 Added RoHS compliance information on page 1 and in the "Product Ordering Information" on page 26 Added the solder reflow temperature to the "Absolute Maximum Stress Ratings" on page 9.
04 05 06
* * * * * *
Sep 2003 Nov 2003 May 2005
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2005 Silicon Storage Technology, Inc. S71209-06-000 5/05
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